Precision creation of inter-gates insulator

ABSTRACT

An ONO-type inter-poly insulator is formed by depositing intrinsic silicon on an oxidation stop layer. In one embodiment, the oxidation stop layer is a nitridated top surface of a lower, and conductively-doped, polysilicon layer. In one embodiment, atomic layer deposition (ALD) is used to precisely control the thickness of the deposited, intrinsic silicon. Heat and an oxidizing atmosphere are used to convert the deposited, intrinsic silicon into thermally-grown, silicon dioxide. The oxidation stop layer impedes deeper oxidation. A silicon nitride layer and an additional silicon oxide layer are further deposited to complete the ONO structure before an upper, and conductively-doped, polysilicon layer is formed. In one embodiment, the lower and upper polysilicon layers are patterned to respectively define a floating gate (FG) and a control gate (CG) of an electrically re-programmable memory cell. In an alternative embodiment, after the middle, silicon nitride of the ONO structure is defined, another layer of intrinsic silicon is deposited, by way of for example, ALD. Heat and an oxidizing atmosphere are used to convert the second deposited, intrinsic silicon into thermally-grown, silicon dioxide. An ONO structure with two thermally-grown, and spaced apart, silicon oxide layers is thereby provided.

CROSS REFERENCE TO PARENT U.S. APPLICATION

The following copending U.S. patent application is owned by the owner ofthe present application, benefit is claimed pursuant to 35 USC §120, andthe disclosure of said application is incorporated herein by reference:Ser. No. 10/718,008 filed Nov. 19, 2003 by Zhong Dong, et al andentitled “Precision Creation of Inter-Gates Insulator.”

CROSS REFERENCE TO CO-OWNED APPLICATIONS

The following copending U.S. patent application is owned by the owner ofthe present application, and its disclosures is incorporated herein byreference:

-   -   (A) Ser. No. 10/071,689 filed Feb. 8, 2003 by Zhong Dong et al        and which is originally entitled, “Floating Gate Nitridation”.

CROSS REFERENCE TO PATENTS

The disclosures of the following U.S. patents are incorporated herein byreference:

-   -   (A) U.S. Pat. No. 6,613,695 B2, issued Sep. 2, 2003 to Pomarede        et al. and entitled “Surface Preparation Prior to Deposition”.

In order to avoid front end clutter, the cross referencing sectioncontinues as (2c) at the end of the disclosure, slightly prior torecitation of the patent claims.

FIELD OF DISCLOSURE

The present disclosure of invention relates generally to semiconductordevices and to the manufacture of the same.

The disclosure relates more specifically to mass production of insulatedgate field effect transistors (IGFET's, MOSFET's) which have plural gateelectrodes separated from one another by electrically insulativematerial. Yet more specifically, it relates to so-called ONO structureswhich can be used to separate stacked polysilicon gates in electricallyre-programmable and nonvolatile memory devices.

DESCRIPTION OF RELATED ART

So-called, FLASH memory devices and alike forms of electricallyre-programmable and nonvolatile memory devices have become commerciallypopular due in part to their ability to store data in a small and denseform factors, their ability to be repeatedly re-programmed, and theirability to retain programmed data in a nonvolatile fashion so that evenwhen power is lost, the stored data is preserved.

One relatively simple format for such an electrically re-programmabletype of nonvolatile memory is known as the vertically-stacked gateconfiguration. In this configuration, a so-called “floating gate” (FG)electrode is insulatively sandwiched between an underlying, tunnelinsulator layer and an overlying, inter-gates insulator (IGI) layer. Aso-called “control gate” (CG) electrode is stacked atop the inter-gatesinsulator (IGI) layer. A channel region with opposed source (S) anddrain (D) regions lies under the tunnel insulator layer.

Because of the way the layers are stacked, the IGI layer (inter-gatesinsulator layer) is sandwiched between the floating gate electrode (FG)and the control gate electrode (CG). This sandwiching of material layerscan create problems as will be further explained shortly. In passing, itis to be observed that other types of more complicated configurations ofgate electrodes are possible, including various staggered gateconfigurations. The simpler, stacked gate configuration will besufficient for describing the improvement disclosed herein.

The insulatively-isolated floating gate (FG) of a staked gate cell isintended to store a certain amount of charge and retain that charge evenwhen external power is turned off. The amount of charge stored on the FGdefines the data state of the memory cell. The state of the memory cellcan be altered by moving charge into the FG for representing a firstdata state and by removing charge from the FG for representing anotherdata state. Different mechanisms may be used for injecting charge intoor removing charge from the FG, including hot carrier injection and/orFowler-Nordheim tunneling. The charged or uncharged state of thefloating gate (FG) can be sensed by applying a cell-read voltageV_(GS-read) to the control gate (CG), where the cell-read voltageV_(GS-read) is selected to cause a first magnitude of current conductionbetween the drain (D) and source (S) regions of the cell when thefloating gate (FG) is in a first programmed state and to cause no or adifferent magnitude of I_(DS) to flow when the floating gate (FG) is inanother programmed state. (Some devices store multiple data bits percell, where each of different amounts of charge trapped within the FGrepresents a different multi-bit pattern.)

It is important, for purposes of carrying out the various read and writeoperations of floating gate type memory cells (e.g., stacked gatecells), to establish an appropriate pattern of electric fieldintensities across the insulators that surround the charge-storing,floating gate (FG). These electric fields (E-fields) may be establishedby generating correspondingly appropriate voltages between the controlgate (CG), the drain (D), the source (S) and/or substrate (U) regions ofthe memory cell. Those skilled in the art will appreciate that electricfield intensity in dielectric insulators is usually a function ofvoltage difference (V) divided by dielectric thickness (d) andmultiplied by dielectric constant (E=kV/d). In order to get consistentresults from mass produced devices, it is important to maintain precisecontrol over the dielectric thickness (d) and the dielectric constant(k) of the various insulators which surround the FG of each cell so thatsame results will occur in one device and the next for a given controlgate voltage (V_(CG)). Stated otherwise, consistently same capacitivecoupling should occur from one mass produced device to the next betweenthe CG, the FG, the source (S), the drain (D) and the substrate (U).

Persons skilled in the art will appreciate that most insulators are notperfect. A small amount of leakage current can undesirably flow throughthem. They can undergo high voltage breakdown. Contaminating chemicalscan pass through pinhole or other defects in the insulators. Muchprogress has been made in the formation of the so-called, thermal gateoxide insulator that lies between the substrate and the floating gate(FG). However, the inter-gates insulator layer (IGI) that is sandwichedbetween the FG and the CG still suffers from problems.

The inter-gates insulator layer (IGI) is particularly prone to problemswith leakage current and breakdown. Practitioners in the art havedeveloped a so-called ONO solution. According to basic ONO practice,after the material for the floating gate (FG) is deposited (typically itis doped polysilicon), three insulative layers are vapor deposited insequence. The three insulative layers are respectively composed ofsilicon-Oxide, silicon-Nitride and silicon-Oxide; hence the ONO acronym.The material for the control gate (CG) is then deposited (typically itis doped polysilicon) on top of the ONO structure. The ONO structure isadvantageous because silicon-nitride (Si₃N₄) generally has a greaterdielectric constant (k) than does silicon dioxide (SiO₂). The higherdielectric constant of the silicon-Nitride layer in the ONO stack letscell designers use lower gate voltages than would otherwise be possiblefor an equal thickness of insulator material made of only silicon-oxide.It is desirable to keep gate voltages relatively small. The ONO approachallows this to happen.

Despite improvements in vapor deposition techniques, the ONO approachstill suffers from the existence of small leakage currents between theFG and the CG. Precise control of ONO thickness and material qualitywithin the ONO stack also remains a problem.

One improvement over the conventional ONO structure is disclosed in ourabove-cited U.S. patent application Ser. No. 10/071,689 (“Floating GateNitridation”). Briefly, nitrogen is introduced into the top surface ofthe doped-polysilicon FG layer after that layer is deposited. Thenitrogen concentration is about 1% to about 20% atomic in the top of theFG layer after nitridation. A higher quality silicon oxide is formedatop the nitridated FG layer, in one embodiment of Ser. No. 10/071,689,by exposing the nitridated, doped-polysilicon to an oxidizingatmosphere. This consumes silicon atoms out of the nitridated region andcreates an Si_(x)O_(y) layer atop thesilicon-depleted-and-nitrogen-containing layer below. Thenitrogen-containing layer below acts as an oxidation stop. The techniqueof Ser. No. 10/071,689 can therefore provide a NONO insulator structurewith enhanced insulative properties. Room for yet further improvement isnonetheless available.

INTRODUCTORY SUMMARY

Structures and methods may be provided in accordance with the presentdisclosure of invention for improving over the above-described art.

More specifically, in accordance with one set of aspects of the presentdisclosure, the upper surface of a silicon floating gate (FG) isnitridated to thereby define a non-stoichiometric silicon nitride(Si_(x)N_(y)) surface having a nitrogen content of at least 5% (atomic),and more preferably about 10% to 20% (atomic). This nitridated surfacewill serve as an oxidation stop. A thin film of intrinsic (essentiallyundoped) silicon is then deposited on the Si_(x)N_(y) surface. Heat andan oxidizing atmosphere are then provided for converting the deposited,intrinsic silicon into a thermally-grown oxide layer (Si_(m)O_(n), wheretypically m=1 and n=2). The non-stoichiometric silicon nitride(Si_(x)N_(y)) layer blocks oxidation below it. Some of the silicon atomsin the Si_(x)N_(y) layer may be consumed by the oxidizing atmosphere inthe process to create further amounts of thermally generated, siliconoxide (Si_(w)O_(v), where typically w=1 and v<2). At least part of thethermally-formed, silicon oxide structure is dopant-free SiO₂ as aresult of the earlier deposition of the intrinsic silicon film.

In one set of embodiments, atomic layer deposition (ALD) is used forprecisely controlling the thickness of the intrinsic silicon film. Afteroxidation of the intrinsic silicon film, a film of stoichiometricsilicon nitride (Si₃N₄) is vapor deposited. Thereafter a silicon oxidefilm is formed to complete the NONO structure. A control gate (CG) isformed over the NONO structure. Charge leakage between the floating gate(FG) and the control gate (CG) of this embodiment is reduced because thethermally-grown and dopant-free oxide portion of the NONO structureexhibits good insulating properties, particularly because it is grownfrom intrinsic silicon.

In accordance with an overlapping or somewhat separate aspect of thepresent disclosure, the lower surface of a control gate (CG) hasthermally-grown oxide formed directly under it. In the course of formingan ONO or NONO structure in accordance with this aspect, a thin film ofintrinsic silicon (essentially dopant-free) is deposited after theupper, film of stoichiometric silicon nitride (Si₃N₄) is vapor depositedto define the middle nitride layer of the ONO or NONO structure. Thestructure is then subjected to an oxidizing atmosphere so as to convertthe intrinsic silicon film into a thermally-grown and essentiallydopant-free oxide layer. The stoichiometric silicon nitride (Si₃N₄)layer blocks oxidation below it. In one set of embodiments, atomic layerdeposition (ALD) is used for precisely controlling the thickness of theupper intrinsic silicon film. After oxidation of the upper intrinsicsilicon film, the material (e.g., doped polysilicon) of the control gate(CG) is vapor deposited. In an overlapped embodiment, both the upper andlower silicon oxide layers of a NONO structure are thermally-grown fromintrinsic silicon and both of the intrinsic silicon layers are providedby way of ALD.

An insulating structure in accordance with the disclosure comprises: (a)an oxidation stop layer; and (b) a thermally-grown, intrinsic, siliconoxide layer which has been grown from ALD deposited intrinsic, siliconthat had been deposited on said oxidation stop layer.

An isolation providing method in accordance with the present disclosurecomprises: (a) defining an oxidation stop layer above aconductively-doped, first semiconductor layer; (b) providing anintrinsic silicon layer on the oxidation stop layer; (c) oxidizing atleast a sublayer portion of the intrinsic silicon layer so as to therebycreate a thermally-grown, intrinsic silicon oxide sublayer over thefirst semiconductor layer; and (d) disposing a conductively-doped,second semiconductor layer above the intrinsic silicon oxide sublayer sothat the intrinsic silicon oxide sublayer provides isolation between thefirst and second conductively-doped, semiconductor layers.

Other aspects of the disclosure will become apparent from the belowdetailed description.

DESCRIPTION OF THE DRAWINGS

The below detailed description section makes reference to theaccompanying drawings, in which:

FIG. 1 is a conceptual schematic diagram showing an environment in whichit is valuable to form a good, but relatively thin, electrical insulatorbetween two, conductively-doped semiconductor layers (e.g., to therebyform an inter-poly or inter-gates insulator);

FIG. 2 is a cross sectional schematic diagram showing how a conventionalONO structure is formed to serve as an inter-poly insulator betweenstacked gates of a nonvolatile memory device;

FIG. 3A is a cross sectional schematic diagram showing a first step(poly-1 deposition) in an IGI fabrication method in accordance with thepresent disclosure;

FIG. 3B is a cross sectional schematic diagram showing a second step(nitridation) in a continuation of the fabrication method introduced byFIG. 3A;

FIG. 3C is a cross sectional schematic diagram showing a third step(precise Si deposition) in a continuation of the fabrication method ofFIG. 3B;

FIG. 3D is a cross sectional schematic diagram showing a fourth step(beginning of oxidation of precisely deposited and intrinsic Si) in acontinuation of the fabrication method of FIG. 3C;

FIG. 3E is a cross sectional schematic diagram showing continuation ofthe oxidation begun by the step of FIG. 3D;

FIG. 3F is a cross sectional schematic diagram showing an optionalfurther continuation of the oxidation begun by the step of FIG. 3D;

FIG. 3G is a cross sectional schematic diagram showing a fifth step (CVDdeposition of SiN) in a continuation of the fabrication method of FIGS.3D-3F;

FIG. 3H is a cross sectional schematic diagram showing a set of furthersteps (CVD deposition of SiO and CVD deposition of CG) in a continuationof the fabrication method of FIG. 3G;

FIG. 4A is a cross sectional schematic diagram showing an alternatesixth step (second precise deposition of intrinsic silicon) in acontinuation of the fabrication method of FIG. 3G;

FIG. 4B is a cross sectional schematic diagram showing an alternatefurther step (begin oxidation of second precisely deposited Si) in acontinuation of the fabrication method of FIG. 4A;

FIG. 4C is a cross sectional schematic diagram showing continuation ofthe oxidation begun by the step of FIG. 4B;

FIG. 4D is a cross sectional schematic diagram showing an optionalfurther continuation of the oxidation begun by the step of FIG. 4B;

FIG. 4E is a cross sectional schematic diagram showing a yet furtherstep (CVD deposition of doped poly-silicon) in a continuation of thefabrication method of FIG. 4A; and

FIG. 4F is a cross sectional schematic diagram showing an alternatestructure in which the step of FIGS. 3C-3F have been replaced by CVDdeposition of silicon oxide.

DETAILED DESCRIPTION

FIG. 1 is a conceptual schematic diagram showing in cross section, anenvironment 100 in which it may be useful to form a good, but thin,electrical insulator 140 between two, conductively-doped semiconductorlayers, 130 and 150. More specifically, the not-to-scale diagram of FIG.1 shows the structure of a stacked-gate memory cell. The cell 105 isintegrally formed as part of a monolithically integrated circuit havinga common substrate 110. In one embodiment, the substrate 110 includesdoped monocrystalline silicon. Spaced apart source (S) 111 and drain (D)112 regions may be formed by implant of suitable doping about anoppositely doped, channel portion 115 of the monocrystalline siliconsubstrate 110. A relatively thin oxide layer (so-called tunnel oxide, orTOX) may be provided on the surface of the channel portion 115.Typically, the TOX is thermally grown from the underlying,monocrystalline silicon 115. (The TOX may be thermally grown prior tothreshold implant of dopants into channel portion 115 and prior to theimplant doping of the source and drain regions, 111-112. Doping isunderstood to include the provision of impurity atoms such as boron,arsenic or phosphorus into the semiconductor crystal structure to impartP-type or N-type conductivity to the doped semiconductor region.)

A first, electrically-conductive gate electrode 130 is formed over theTOX layer 120, typically by chemical vapor deposition (CVD) of doped,polysilicon. A so-called, inter-poly or inter-gates insulator (IPI orIGI) 140 is formed over the first gate electrode 130. A second,electrically-conductive gate electrode 150 is formed over the IGI layer140. Typically, the second gate electrode 150 is fabricated by CVD ofdoped polysilicon.

Patterning of the gate electrodes (130, 150) may occur before or afterthe source/drain doping implants. Typically, the source/drain dopingimplants occur after patterning so as to provide for self-alignment withthe patterned gates. Post-patterning sidewalls of the first and/orsecond gate electrodes 130-150 as well as those of the IGI layer 140 maybe surrounded by additional insulative material (e.g., additionalsilicon dioxide) and/or may be embedded in shallow-trench isolation(STI) wells as may be appropriate. No specific top-view patterning isintended by the conceptual side view of FIG. 1. During devicefabrication, electrical connections are typically made to the secondgate electrode 150 (hereafter also, the control gate or CG), to thesource region (S) 111, to the drain region (D) 112, and to the substrate(U) 110, but not to the first gate electrode 130. Theinsulation-surrounded first gate electrode 130 is commonly referred toas the floating gate (FG).

Those skilled in the art will appreciate that the floating gate (FG) 130is typically used to nonvolatiley store trapped charge 135. This charge135 may be injected into the FG 130 or removed from the FG 130 by way ofhot carrier injection or Fowler-Nordheim tunneling, usually with theinjected/extracted moving or tunneling through the tunnel oxide (TOX)120. When charge is being purposefully injected into the FG 130 or beingremoved from it, a relatively large, writing voltage (V_(GU)) istypically established between the control gate (CG) 150 and thesubstrate (U) 110. Charge then tunnels or otherwise crosses through thethin TOX layer 120 in the desired direction to add to, or subtract fromthe amount of charge already present in the floating gate (FG) 130.

It is desirable to have precise control over the amount of charge beingmoved into or being removed from the FG 130 during a write cycle becausethe amount of charge remaining in the FG after a write cycle willdetermine the memory state of the cell 105. More specifically, the stateof the floating gate (FG) will be generally sensed by applying acell-read voltage V_(GS-read) between the control gate (CG) and thesource region (S) 111 or another reference node. The magnitude of thecell-read voltage V_(GS-read) will be pre-selected to cause a firstmagnitude of current, I_(DS) (not shown) to flow between the drain (D)and source (S) regions of the cell when the floating gate (FG) is in afirst programmed state (e.g., representing a binary 1) and to cause noor a different magnitude of I_(DS) to flow when the floating gate (FG)is in another programmed state (e.g., representing a binary 0). Thecharged state of the FG 130 is not limited to just two distinct states.Some memory devices are designed to store multiple data bits per cell,where each of different amounts of charge 135 trapped within the FGrepresents a different one of the multi-bit patterns (e.g., 00, 01, 10and 11). The above are just examples. The amount of charge 135 trappedwithin the FG 130 may alternatively represent an analog value.

The amount of charge moved into or out of the FG 130 during a writecycle is often determined by a number of factors including thedistribution and intensity of electric flux lines through the TOX 120and the composition and physical dimensions of the TOX. The latter,electric flux lines through the TOX are in their turn, often defined bythe voltages present on the control gate (CG) 150, the drain (D) 112,the source (S) 111, and the substrate (U) 110 regions of the memory cell105. The electric flux lines (not shown) are further defined by thecomposition and physical dimensions of the IPI/IGI layer 140. Morespecifically, those skilled in the art will appreciate that electricfield intensity in the dielectric insulator or insulators of the IPI/IGIlayer 140 will usually be a function of voltage gradient (V) across eachof the insulators in the IGI, where the voltages are divided by therespective dielectric thickness (d) and multiplied by the respectivedielectric constant (k) of the insulators. This may be roughly expressedas E=kV/d. (In actual practice, a more detailed analysis is oftenconducted using Maxwell's equations. There is no need to delve into suchdetails here.)

It may be understood from the above that mass production fabrication ofa multi-gate cells such as 105 shown in FIG. 1 will often call forprecise control over the respective dielectric thicknesses (d) and therespective dielectric constants (k) of the various insulators which areprovided around the FG 130. Precision is desired so that same resultswill occur in one device and the next for a given control gate voltage(V_(CG)) in combination with other voltages and further factors (e.g.,temperature). In order to get such consistent results in mass produceddevices, it is important to maintain consistency with respect to thedimensions and compositions of the insulators that that form the IGIlayer 140 and the TOX 120. Stated otherwise, consistently samecapacitive coupling should occur from one mass produced device to thenext between the CG, the FG, the source (S), the drain (D) and thesubstrate (U).

Persons skilled in the art will appreciate that most insulators are notperfect. A small amount of leakage current can undesirably flow throughthem. They can undergo high voltage breakdown. Contaminating chemicalscan pass through pinhole or other defects in the insulators. Theinter-gates insulator layer (IGI) 140 is particularly prone to problemswith leakage current because, unlike the TOX layer 120, the IGI 140 isgenerally sandwiched between two layers of doped polysilicon: the CG 150and the FG 130. Artisans have learned that the IGI 140 will not be verygood if it made through brute-force oxidation of doped polysilicon inthe FG layer 130. Practitioners in the art have developed a so-calledONO solution.

The conventional ONO solution is illustrated in the cross sectional view(not-to-scale) of FIG. 2. After TOX (220) is grown to a first thickness(Z1) and the doped polysilicon material for the floating gate (FG) 230is deposited, three insulative layers are deposited in sequence by meansof CVD. The three insulative layers are respectively composed ofsilicon-Oxide (242, having thickness Z2), silicon-Nitride (244, havingthickness Z3) and silicon-Oxide (246, having thickness Z4); hence theONO acronym (240). The material for the control gate (CG) 250 is thendeposited (typically it is doped polysilicon) on top of the ONOstructure 240. Because stoichiometric silicon-nitride (Si₃N₄) generallyhas a greater dielectric constant (k) than does silicon dioxide (SiO₂)or other silicon oxides (Si_(x)O_(y)), the higher dielectric constant ofthe silicon-Nitride layer 244 in the ONO stack 240 lets cell designersuse lower gate voltages (V_(GS-read), V_(GU-write)) than would otherwisebe necessary for an equal thickness (Z2+Z3+Z4) of insulator materialmade of only silicon-oxide. It is desirable to keep gate voltagesrelatively small. Thus the ONO solution has become very popular.

Despite improvements with vapor deposition techniques, the ONO approachstill suffers from the presence of leakage current 137 (I_(LEAK))between the FG (130, 230) and the CG (150, 250). Precise control of ONOthickness (Z2+Z3+Z4) and material quality within the ONO stack 240remains a problem.

One improvement over the conventional ONO structure 240 (FIG. 2) isdisclosed in our above-cited U.S. patent application Ser. No. 10/071,689(“Floating Gate Nitridation”). Briefly, a small amount of nitrogen(e.g., about 1%-20% atomic) is introduced into the top surface of thedoped-polysilicon FG layer after that layer is deposited. The nitridatedlayer is subjected to a high temperature oxygen-containing atmosphere.Silicon atoms in the nitridated layer are scavenged by the hotoxygen-containing atmosphere to form a thermally-grown, silicon oxide.The increased concentration of nitrogen in the silicon-scavenged areastops the oxidation front from moving deeper into the FG layer. A higherquality of silicon oxide may be formed atop the nitridated FG layer bythis thermally-growth technique. The technique provides a NONO insulatorstructure with enhanced insulative properties. Room for yet furtherimprovement is available.

FIG. 3A is a cross sectional schematic diagram showing a first step 301(Poly-1 deposition) in an IGI fabrication method in accordance with thepresent disclosure. Briefly, after TOX layer 320 is thermally-grown tothickness Z1′, a doped polysilicon layer 330 is deposited to thicknessZ5. In one embodiment, thickness Z5 is in the range of about 1000 Å toabout 2000 Å. TOX thickness Z1′ is in the range of about 10 Å to about100 Å, and in a more specific set of embodiments, Z1′ is in the range ofabout 30 Å to about 50 Å. The source and drain regions 311, 312 aretypically not yet have formed at this stage and are shown in phantom(dashed lines) simply to provide a point of reference for what willlater develop around channel region 315 of the monocrystalline siliconsubstrate, 310.

FIG. 3B is a cross sectional schematic diagram showing a second step 302(nitridation) in a continuation of the fabrication method introduced byFIG. 3A. A nitrogen implant 392 and/or other means are used to introducenitrogen atoms into top region 335 of the doped polysilicon layer 330.This forms an Si_(x)N_(y) composition in region 335 to a depth Z7 belowthe surface, where y is sufficiently large to provide a concentration ofat least 1% atomic nitrogen, and better yet, at least about 5% atomicnitrogen, and more preferably, at least about 10% atomic nitrogen.Various techniques can be used to form an oxidation-stopping gradientwherein nitrogen concentration in region 335 rises to as high as about20% to 30% atomic nitrogen. Nitridation by way of ion implant mayinclude the application to FG layer 330 (FIG. 3A) of a dose of 10¹³ to10¹⁵ atoms/cm² or higher of nitrogen at energies in the range 1 KeV toabout 30 KeV to form a homogenous or graded Si_(x)N_(y) composition inregion 335 to the Z7 depth. Z7 can be as little as about 10 Å and shouldbe no more than about 30 Å. The ion implant may be followed by a thermalanneal in an inert atmosphere at 850° C. to about 1000° C. for about 10to 60 seconds. A Z7 thickness of as little as about 5 Å may be obtainedif alternate nitridation techniques are used such as DPN (DecoupledPlasma Nitridation) or RPN (Remote Plasma Nitridation) are used. Acombination of ion implant and DPN or RPN may be used, followed byoptional thermal anneal, to provide a nitrogen concentration gradientwhere nitrogen density increases moving deeper down the Z7 depth. Therelatively high concentration of nitrogen will be used to slow down orstop a descending oxidation front (342 in FIG. 3D) as will be seenbelow.

While FIG. 3B shows the surface layer 335 as having just a Si_(x)N_(y)composition, it is within the contemplation of the disclosure toincorporate other atoms within this region including an oxygen gradientwhose oxygen density decreases moving deeper down the Z7 depth while atthe same time nitrogen concentration increases when moving deeper downthe Z7 depth. The oxygen atoms may be ion implanted or otherwiseintroduced into surface region 335 together with nitrogen atoms. The topof surface region 335 may be treated to enhance surface chemisorption ina subsequent ALD step 303 (FIG. 3C).

Referring to FIG. 3C, in a next step 303, a layer of intrinsic silicon341 is deposited to a thickness Z8 on top of the nitridated region 335′.Deposition thickness Z8 can be as small as about 15 Å to about 50 Å. Itcan also be thicker if desired. In one embodiment, Atomic LayerDeposition (ALD) is used to form the 15 Å-50 Å thickness of theessentially dopant-free, silicon layer 341. Other precision forms ofdeposition 393 of the intrinsic silicon may be alternatively used. Thoseskilled in the art will appreciate that ALD is related to CVD (chemicalvapor deposition) except that only one reactant at a time ispulse-supplied through the deposition chamber. A first of thepulse-supplied reactants (e.g., dichlorosilane SiH₂Cl₂) adheres to thesubstrate surface as a chemisorbed monolayer. The second pulse-suppliedreactant (e.g., monosilane SiH₄) is provided to react with thechemisorbed monolayer of the first reactant to thereby form a monolayerof the desired reaction product (e.g., silicon). The process ofpulse-supplying the first reactant and then the second is repeated Ntimes until a product layer that is N monolayers thick is formed. Thethickness of an ALD-defined layer such as 341 can be digitallycontrolled by the setting of the deposition repetition factor N. Thus,the thickness Z8 of ALD-defined layer 341 can be precisely controlled.

Referring to FIG. 3D, in a next step 304, an oxygen-containingatmosphere 394 is supplied to the top surface of layer 341 at anappropriate oxidizing temperature, such as about 750° C. to about 850°C. The hot oxygen-containing atmosphere 394 converts the exposed,intrinsic Si 341 (FIG. 3C) into thermally-grown SiO₂ 343. FIG. 3D showsthe oxidation front 342 as having advanced only partially down intooriginal layer 341 thereby still leaving some intrinsic Si in region341′. The thickness, Z8′ of the remaining intrinsic-Si 341′ is less thanthe original thickness Z8 of FIG. 3C. Total thickness Z9 of thepartially oxidized silicon is greater than Z8 though, because thethickness of thermally-grown oxide is typically twice that of theoriginal silicon material.

Referring to FIG. 3E, in a next state 305, the oxygen-containingatmosphere 394′ continues to be supplied to the top surface of oxidizinglayer 343′. Thickness Z9′ is about twice that of original thickness Z8of the original, intrinsic silicon layer 341 (FIG. 3C). When theoxidation front 342′ reaches the nitridated region 335′, the rate ofoxidation slows substantially because silicon nitride acts as aretardant to further oxidation. The degree of retardation will depend onthe concentration of nitrogen atoms present as the oxidation front 342′descends down thickness Z7 and continues to bind oxygen to availablesilicon atoms.

Referring to FIG. 3F, in an optional next state 306, theoxygen-containing atmosphere 394″ has continued to be supplied to thetop surface of oxidized upper layer 343″. Some of the silicon atoms thatwere in the Si_(x)N_(y) layer 335′ of state 305 (FIG. 3E) have beenscavenged by the oxidizing process to form a thermally-grown,Si_(w)O_(v) layer 344 where the w/v ratio may be greater than 1/2.Underlying region 335″ has an increased nitrogen concentration and actsas an oxidation stop. The thickness Z10 of the thermally-grown,Si_(w)O_(v) layer 344 may vary and may be in the range of, for example,0-10 Å. Of importance, during the time that region 335″ acts as anoxidation stop and the oxygen-containing atmosphere 394″ continues to besupplied to the top surface of oxidized layer 343″ at an appropriateoxidizing temperature (e.g., about 750° C.-850° C.), the stoichiometricbonding of oxygen atoms to silicon atoms in dopant-free region 343″continues to become more perfected and as a result, more high qualitySiO₂ material is provided in region 343″. Region 343″ therefore becomesa high quality insulating region of precise thickness, particularlybecause it is essentially free of dopants (P or N type) and because itis thermally-grown and because the thickness of its precursor siliconmaterial (341 of FIG. 3C) was precisely defined by ALD deposition oranother, alike precision deposition method. Although ALD is disclosed asa precision deposition method, it is within the contemplation of thedisclosure that less precise deposition methods such as CVD may be usedto provide the intrinsic silicon 341 on top of nitridated region 335′(FIG. 3C).

Referring to FIG. 3G, in a next step 307, a silicon nitride layer 345(e.g., Si₃N₄) is deposited (by CVD, ALD or otherwise) to a thickness Z11on top of the thermally-grown SiO₂ layer 343″. Typically Z11 will be inthe range of about 50 Å to about 100 Å. It is within the contemplationof the disclosure to alternatively use other high-K dielectrics in placeof Si_(x′)N_(y′) in layer 345. The good insulative quality of thethermally-grown, SiO₂ layer 343″ reduces the leakage current demands onthe overlying, higher-K dielectric layer 345. Examples of alternativehigher-K dielectric materials include SiON. The SiON could bealternatively formed by nitridating the top surface of layer 343″ andthereby reducing thickness parameter Z9″.

Referring to FIG. 3H, in a next step 308, a silicon oxide layer 346(Si_(x″)O_(y″)) is deposited (by CVD, ALD or otherwise) to a thicknessZ13 on top of the higher-K dielectric layer 345 (e.g., Si_(x′)N_(y′)).This is followed in a subsequent step 309 by deposition (via CVD orotherwise) to a thickness Z15, of the polycrystalline silicon materialthat will define the conductively doped, CG layer 350. Theconductivity-defining dopants of layer 350 may be introduced during thedeposition of the polycrystalline silicon material of CG layer 350and/or afterwards by ion implant.

FIG. 3H illustrates the completed, multigate structure 360 in which two,conductively doped, polysilicon gate electrodes, 330′ (FG) and 350 (CG)are insulated from each other by a NONO structure 340 that includes atleast one, thermally-grown SiO₂ layer 343″ that is essentially free ofdopants. This thermally-grown SiO₂ layer 343″ provides enhancedprotection against leakage currents. The illustrated NONO structure 340also includes the nitridated lower region 335″, the CVD-Si_(x′)N_(y′),layer 345 and the CVD-Si_(x″)O_(y″) layer 346. The thermally-generated,Si_(w)O_(v) layer 344 is optional.

Referring to FIG. 4A, an alternate process path is shown in crosssection following the vapor deposition of silicon nitride layer 345(e.g., Si₃N₄) in FIG. 3G. The concentration of nitrogen atoms at the topsurface of the Si_(x′)N_(y′) layer 345 of FIG. 4A may be substantiallythe same as that deeper in the layer, or, if layer 345 is not completelystoichiometric silicon nitride (not all Si₃N₄) then the concentration ofnitrogen atoms at the top surface may be augmented with furthernitridation via ion implant, DPN (Decoupled Plasma Nitridation) or RPN(Remote Plasma Nitridation) so that concentration of nitrogen withinregion 345′ is at least about 5% atomic nitrogen, and more preferably,at least about 10% atomic nitrogen. Various techniques can be used toform an oxidation-stopping gradient wherein nitrogen concentration inregion 345′ rises to as high as about 20% to 30% atomic nitrogen.

In subsequent step 407, a layer of intrinsic silicon 446 is deposited toa thickness Z12 on top of the nitrogen-containing region 345′.Deposition thickness Z12 can be as small as about 15 Å to about 50 Å. Itcan also be thicker if desired. In one embodiment, Atomic LayerDeposition (ALD) is used to form the 15 Å-50 Å thickness of theessentially dopant-free, silicon layer 446. Other precision forms ofdeposition 496 of the intrinsic silicon may be alternatively used.

Referring to FIG. 4B, in a next step 408, an oxygen-containingatmosphere 497 is supplied to the top surface of layer 446 at anappropriate oxidizing temperature, such as about 750° C. to about 850°C. The hot oxygen-containing atmosphere 497 converts the exposed,intrinsic Si 446 (FIG. 4A) into thermally-grown SiO₂ 443. FIG. 4B showsthe oxidation front 442 as having advanced only partially down intooriginal layer 446 thereby still leaving some intrinsic Si in region446′. The thickness, Z12′ of the remaining intrinsic-Si 446′ is lessthan the original thickness Z12 of FIG. 4A. Total thickness Z14 of thepartially oxidized silicon is greater than Z12 though, because thethickness of thermally-grown oxide is typically twice that of theoriginal silicon material.

Referring to FIG. 4C, in a next state 409 of the oxidation process 408started in FIG. 4B, the oxygen-containing atmosphere 497′ continues tobe supplied to the top surface of oxidizing layer 443′. Thickness Z14′is about twice that of original thickness Z12 of the original, intrinsicsilicon layer 446 (FIG. 4A). When the oxidation front 442′ reaches thenitrogen-containing region 345′, the rate of oxidation slowssubstantially because silicon nitride acts as a retardant to furtheroxidation. The degree of retardation will depend on the concentration ofnitrogen atoms present as the oxidation front 442′ descends downthickness Z11 of the silicon nitride layer and continues to bind oxygento available silicon atoms.

Referring to FIG. 4D, in an optional next state 410 of the oxidationprocess 408 started in FIG. 4B, the oxygen-containing atmosphere 497″has continued to be supplied to the top surface of oxidized upper layer443″. Some of the silicon atoms that were in the Si_(x)N_(y) layer 435′of state 409 (FIG. 4C) have been scavenged by the oxidizing process toform a thermally-grown, Si_(w)O_(v) layer 444 where the w/v ratio may begreater than 1/2. Underlying region 345″ has an increased nitrogenconcentration due to the silicon scavenging and acts as an oxidationstop. The thickness Z16 of the thermally-grown, Si_(w)O_(v) layer 444may vary and may be in the range of, for example, 0-10 Å, or morespecifically if present, about 5 Å to about 10 Å. Of importance, duringthe time that region 345″ acts as an oxidation stop and theoxygen-containing atmosphere 497″ continues to be supplied to the topsurface of oxidized layer 443″, this being done at an appropriateoxidizing temperature (e.g., about 750° C.-850° C.), the stoichiometricbonding of oxygen atoms to silicon atoms in dopant-free region 443″continues to become more perfected and as a result, more high qualitySiO₂ material is provided in region 443″. Region 443″ therefore becomesa high quality insulating region of precise thickness, particularlybecause it is essentially free of dopants (P or N type) and because itis thermally-grown and because the thickness of its precursor siliconmaterial (446 of FIG. 4A) was precisely defined by ALD deposition 496 oranother, alike precision deposition method. Although ALD is disclosed asa precision deposition method, it is within the contemplation of thedisclosure that other deposition methods such as CVD (even if they maybe less precise) may be used to provide the intrinsic silicon 446 on topof nitrogen-containing region 345′ (FIG. 4A).

Referring to FIG. 4E, in a subsequent step 411, the polycrystallinesilicon material that will define the conductively doped, CG layer 450is provided (e.g., via CVD or otherwise) to a thickness Z15′. Theconductivity-defining dopants of layer 450 may be introduced during thedeposition of the polycrystalline silicon material of CG layer 450and/or afterwards by ion implant.

FIG. 4E illustrates the completed, multigate structure 460 in which two,conductively doped, polysilicon gate electrodes, 330′ (FG) and 450 (CG)are insulated from each other by a NONO structure 440 that includes atleast two, thermally-grown SiO₂ layers, 343″ and 443″, that are eachessentially free of dopants. These thermally-grown SiO₂ layers, 343″ and443″, provide enhanced protection against leakage currents. Theillustrated NONO structure 440 also includes the nitridated lower region335″, and the CVD-Si_(z′)-N_(y′) layer 345″. The thermally-generated,Si_(w)O_(v) layer 444 is optional.

Referring to FIG. 4F, an alternate structure 470 is shown wherein theprocess steps of FIGS. 3B-3F have been replaced by CVD deposition ofsilicon oxide to thereby provide layer 447 sandwiched between the FGelectrode 330″ and the Si_(z)N_(y) layer 345″. Source and drain regions411′ and 412′ where implanted after patterning of the FG electrode 330″.CVD-SiO layer 447 provides sidewall and top insulation for the FGelectrode 330″. The overlying parts 345′″-443″ may be bracketed within ashallow-trench isolation well (having HDP-oxide sidewalls, not shown).The resulting ONO structure 440′ within the isolation well includes thethermally-grown and intrinsic, silicon dioxide layer 443″. Layer 443″has high quality SiO₂ and therefore reduces charge leakage between thefloating gate (FG) 330″ and the control gate (CG) 450″. Portion 451″ isan extension of the control gate which is spaced higher up than Z14 andtherefore does not affect electric field concentration near the channel415′ nearly as much as does the descended part of the control gate 450″(the part immediately above SiO₂ thickness Z14).

The present disclosure is to be taken as illustrative rather than aslimiting the scope, nature, or spirit of the subject matter claimedbelow. Numerous modifications and variations will become apparent tothose skilled in the art after studying the disclosure, including use ofequivalent functional and/or structural substitutes for elementsdescribed herein, use of equivalent functional couplings for couplingsdescribed herein, and/or use of equivalent functional steps for stepsdescribed herein. Such insubstantial variations are to be consideredwithin the scope of what is contemplated here. Moreover, if pluralexamples are given for specific means, or steps, and extrapolationbetween and/or beyond such given examples is obvious in view of thepresent disclosure, then the disclosure is to be deemed as effectivelydisclosing and thus covering at least such extrapolations.

2c. Cross Reference to Related Other Publications

The following publications are cited here for purposes of reference andtheir disclosures are incorporated by reference:

-   -   A) U.S. published application No. 2003/0082300 A1 published May        1, 2003, entitled “Improved Process for Deposition of        Semiconductor Films”, and naming as inventors: Todd et al.    -   (B) U.S. published application No. 2003/0166318 A1 published        Sep. 4, 2003, entitled “Atomic Layer Deposition of Capacitor        Dielectric”, and naming as inventors: Zheng et al.        2d. Reservation of Extra-Patent Rights, Resolution of Conflicts,        and Interpretation of Terms

After this disclosure is lawfully published, the owner of the presentpatent application has no objection to the reproduction by others oftextual and graphic materials contained herein provided suchreproduction is for the limited purpose of understanding the presentdisclosure of invention and of thereby promoting the useful arts andsciences. The owner does not however disclaim any other rights that maybe lawfully associated with the disclosed materials, including but notlimited to, copyrights in any computer program listings or art works orother works provided herein, and to trademark or trade dress rights thatmay be associated with coined terms or art works provided herein and toother otherwise-protectable subject matter included herein or otherwisederivable herefrom.

If any disclosures are incorporated herein by reference and suchincorporated disclosures conflict in part or whole with the presentdisclosure, then to the extent of conflict, and/or broader disclosure,and/or broader definition of terms, the present disclosure controls. Ifsuch incorporated disclosures conflict in part or whole with oneanother, then to the extent of conflict, the later-dated disclosurecontrols.

Unless expressly stated otherwise herein, ordinary terms have theircorresponding ordinary meanings within the respective contexts of theirpresentations, and ordinary terms of art have their correspondingregular meanings within the relevant technical arts and within therespective contexts of their presentations herein.

Given the above disclosure of general concepts and specific embodiments,the scope of protection sought is to be defined by the claims appendedhereto. The issued claims are not to be taken as limiting Applicant'sright to claim disclosed, but not yet literally claimed subject matterby way of one or more further applications including those filedpursuant to 35 U.S.C. §120 and/or 35 U.S.C. §251.

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 22. A method of forming insulation comprising:(a) defining an oxidation stop layer in a top portion of a firstconductively-doped semiconductor layer; (b) providing an essentiallyundoped semiconductor layer on the first conductively-dopedsemiconductor layer and above the first oxidation stop layer; (c)oxidizing the essentially undoped semiconductor layer so as to therebycreate a corresponding, essentially undoped and thermally-grown, firstoxide sublayer over the first conductively-doped semiconductor layer;and (d) disposing a second conductively-doped semiconductor layer abovethe first oxide sublayer so that the first oxide sublayer provideselectrical insulation between the first and second conductively-dopedsemiconductor layers.
 23. The insulation forming method of claim 22wherein: (a.1) said defining of the oxidation stop layer includesintroducing nitrogen into the top portion of a first conductively-dopedsemiconductor layer.
 24. The insulation forming method of claim 23wherein: (a.1a) said introducing of the nitrogen into the top portionincludes causing the introduced nitrogen to exhibit a concentrationgradient.
 25. The insulation forming method of claim 22 wherein: (a.1)said defining of the oxidation stop layer includes defining an adhesionsurface on the top portion of a first conductively-doped semiconductorlayer for adhering to the essentially undoped semiconductor layer.
 26. Amethod of providing a high quality silicon dioxide layer atop a firstconductively-doped semiconductor layer, the method comprising: (a)introducing nitrogen into the first conductively-doped semiconductorlayer through a top portion of the first conductively-dopedsemiconductor layer; (b) adhering an essentially undoped silicon layerto the top portion of the first conductively-doped semiconductor layer;(c) thermally oxidizing the adhered and essentially undoped siliconlayer at least until a corresponding oxidation front of said thermaloxidizing step reaches the nitrogen introduced into the firstconductively-doped semiconductor layer; and (d) continuing said thermaloxidizing step beyond when the corresponding oxidation front reaches theintroduced nitrogen.
 27. The providing method of claim 26 and furthercomprising: (e) disposing a second conductively-doped semiconductorlayer above the thermally oxidized and essentially undoped siliconlayer.
 28. The providing method of claim 27 and further comprising: (f)interposing a silicon nitride layer between the thermally oxidized andessentially undoped silicon layer and the second conductively-dopedsemiconductor layer.
 29. The providing method of claim 28 and furthercomprising: (g) interposing a silicon oxide layer between the siliconnitride layer and the second conductively-doped semiconductor layer.